This invention relates to a method for forming a single crystal silicon layer, and more particularly to an apparatus for growing a single crystal silicon at a desired thickness in a selected portion, and a method for forming a single crystal silicon layer using the same.
As is well known, a dynamic random access memory (DRAM) device includes a cell array portion where a plurality of DRAM cells where each consists of a transistor and a capacitor, are arranged in a matrix form and a peripheral circuit portion which drives the cell array portion to write data in the DRAM cells or to read the stored data from the DRAM cells. The DRAM cell includes a bit line which is electrically connected to the peripheral circuit portion and in accordance with the signal from the peripheral circuit portion, write/read the data in/from the capacitor through the bit line.
FIG. 1 is a sectional view of a typical DRAM cell. An isolation film 2 is formed in a surface of a silicon substrate 1 to define an active region and a transistor 10 including a gate oxide 3, a gate 4 and source and drain regions 6a and 6b is formed in the active region of the substrate 1 defined by the isolation film 2. The reference numeral 5 in drawing designates spacers used in forming the source and drain regions 6a and 6b of a lightly doped drain type.
The first intermediate insulating layer 11 is formed to cover the transistor 10 and then etched to form a first contact hole 12 which exposes the drain region 6b of the transistor 10. A plug 13 for bit line is formed within the first contact hole 12 and a bit line 14 is formed over the first intermediate insulating layer to be contacted with the drain region 6b through the bit line plug 13.
A second intermediate insulating layer 15 is formed over the first intermediate insulating layer 11 including the bit line 14 and then the first and second intermediate insulating layers 11 and 15 are etched to form a second contact hole 16 which exposes the source region 6a. A plug 17 for storage node is formed within the second contact hole 16 and a capacitor 20 is formed over the second intermediate insulating layer 15 to be contacted the source region 6a through the storage node plug 17. The capacitor 20 includes a storage node 18a contacted with the source region 6a through the storage node plug 17, a dielectric film 18b formed over the storage node 18a and a plate node 18c formed over the dielectric film 18b. 
A polysilicon layer doped with conductive impurities, which is to be fabricated with ease, has been used as a material for the bit line and the plug for connecting the drain region of the transistor. However, the doped polysilicon has a low mobility of carrier due to an interface effect between grains. When the doped polysilicon uses for bit line plug, it acts on the factor for reducing the input/output speed of data.
Furthermore, the doped polysilicon that is used for the plug for storage node for electrically connecting the storage node of the capacitor where data are stored to the source region of the transistor, acts on the factor of speed reduction as the plug for the bit line. When the doped polysilicon is used for the plug for storage node, because the charges for data are spontaneously reduced, the desired capacitance is not obtained.
The technology using single crystal silicon for bit line plug and storage node plug instead of polysilicon has been proposed. Because the single crystal silicon has grains arranged in one direction, it can improve the data input/output speed as compared with the polysilicon having grains arranged in multiple directions.
The single crystal silicon is formed by a conventional selective epitaxial growth method. The selective epitaxial growth method utilizes the principle that the growth time of the silicon nucleus is different in accordance with the material of the underlying film. It makes silicon atoms to selectively adsorb over the underlying film made of single crystal silicon and grows the single crystal silicon having the same grain direction as the underlying film.
FIG. 2 is a sectional view for illustrating a method for forming a single crystal silicon layer using a conventional selective epitaxial growth method. A silicon substrate 21 being comprised of single crystal silicon is prepared and an oxide layer 22 is formed to expose a portion of the silicon substrate 21 where a single crystal silicon layer is to be formed and then the silicon substrate 21 is inserted into a single crystal silicon growth apparatus (not shown). A single crystal silicon layer 23 is grown on the exposed portion of the silicon substrate 21 by carrying out a selective epitaxial growth process in the single crystal silicon growth apparatus.
However, because the selective epitaxial growth method is carried out at a high temperature of above 1,000xc2x0 C., it is inapplicable to a semiconductor fabrication process carrying out at a temperature of below 700xc2x0 C. Furthermore, when the single crystal silicon layer is formed by the selective epitaxial growth method, because silicon nucleation sites are formed over the underlying film of single crystal silicon as well as over the undesired portion such as the oxide layer after the lapse of a predetermined time, a polysilicon layer is also grown over the oxide layer so that the desired process result can not be obtained.
In the prior art, while the single crystal silicon is grown on the exposed portion of the silicon substrate, the thermal energy is provided to the silicon substrate including the oxide layer to prevent the polysilicon from preventing over the oxide layer.
The prior method providing the thermal energy to the silicon substrate including the oxide layer prevents the polysilicon from growing on the oxide layer, in case of growing the single crystal silicon at a thickness of below 400 xc3x85. However, in case of growing the single crystal silicon layer at a thickness of above 400 xc3x85, although the prior method provides the thermal energy to the silicon substrate including the oxide layer, the polysilicon layer is grown over the oxide layer. Accordingly, it is difficult to adapt the prior method for forming the single crystal silicon layers for bit line plug and storage node plug having a thickness of above several thousands xc3x85.
It is an object of the present invention to provide an apparatus for growing a single crystal silicon having a desired thickness under the process temperature of below 700xc2x0 C.
It is another object of the present invention to provide a method for forming a single crystal silicon using a single crystal silicon growth apparatus.
According to an aspect of the present invention, there is provided to a single crystal silicon growth apparatus, comprising: a chamber where a silicon substrate is to be inserted; a heat source for rapidly rising a temperature in an interior of the chamber; a cooling line for rapidly dropping a temperature in the interior of the chamber; a gas sprayer for providing a source gas and a purge gas inside the chamber; a gas inflow line connected to the gas sprayer for inflowing the source gas and the purge gas into the gas sprayer; and a gas exhausting line for maintaining the interior of the chamber with a vacuum.
There is also provided to a method for forming a single crystal silicon layer at a selected thickness using a single crystal silicon growth apparatus, comprising the steps of: (a) inserting a silicon substrate where an oxide layer is formed to expose a portion thereof, into a chamber of the single crystal silicon growth apparatus; (b) rapidly raising a temperature of the chamber at 600-700xc2x0 C.; (c) spraying a source gas into the silicon substrate to form a single crystal silicon layer having a thiner thickness than the selected thickness over an exposed portion of the silicon substrate; (d) puging the chamber to rapidly drop a temperature of the chamber at a room temperature; and (e) forming the single crystal silicon layer to the selected thickness by repeatedly carrying out the steps (b) and (d).
There is further provided to a method for forming a single crystal silicon layer at a selected thickness using a single crystal silicon growth apparatus, comprising the steps of: (a) preparing a silicon substrate where an oxide layer is formed to expose a portion thereof; (b) cleaning the silicon substrate; (c) inserting the silicon substrate into a chamber of the single crystal silicon growth apparatus; (b) rapidly raising a temperature of the chamber at 600-700xc2x0 C.; (c) spraying a source gas into the silicon substrate to form a single crystal silicon layer having a thinner thickness than the selected thickness over an exposed portion of the silicon substrate; (d) puging the chamber to rapidly drop a temperature of the chamber at a room temperature; and (e) forming the single crystal silicon layer to the selected thickness by repeatedly carrying out the steps (b) and (d).